Volume 11, Number 21, December 2021

Small Delay Tracing Defect Testing

  Authors

Lakshmaiah Alluri¹ and Hemant Jeevan Magadum², ¹HDG, CDAC, India, ²ITNS, CDAC, India

  Abstract

This Small Delay Tracing Defect Testing detect small delay defects by creating internal signal races. The races are created by launching transitions along simultaneous two paths, a reference path and a test path. The arrival times of the transitions on a ‘convergence’ or common gate determine the result of the race. On the output of the convergence gate, a static hazard created by a small delay defect presence on the test path which is directed to the input of a scan-latch. A glitch detector is added to the scan latch which records the presence or absence of the glitch.

  Keywords

Delay, Defect, detector, glitch, testing.