Volume 9, Number 15, November 2019

Analysis of Faults in an N-Bit Self Checking Register

  Authors

T. Shunbaga Pradeepa and S. Uma Maheswari, Coimbatore Institute of Technology, India

  Abstract

Soft errors which are random errors induced by radiations may be produced due to transient faults and upsets in electronic systems. From the survey, it has been observed that the existing error correcting techniques and models have some limitations. The conventionally used error detection method named Triple Modular Redundancy (TMR) method has large overhead which makes it uneconomical. In this paper, the existing techniques like Time Redundancy based error Detection (TRDED) has been implemented and verified for different intervals of errors. It has been observed that only particular errors can be detected and no corrections are done. The modified circuits abbreviated as SETTOFF can be used for Soft Error and Timing Error Tolerant Flip Flop. These circuits which have both error correction and detection has been implemented and verified for different intervals of time. Since the chances of induced errors are increasing, there is a great necessity for developing a technique to provide more reliability and performance. Targeting towards the above features, self-checking register architecture for multi-bit error detection has been proposed and analyzed using Xilinx ISE Simulator for transient fault occurrence and has been analyzed.

  Keywords

Transient Fault, Self-checking register, Single Event Upset (SEU), Multi bit error detection, Single Event Transient (SET)

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