Volume 13, Number 5

Comparison of GPU and FPGA Hardware Acceleration of Lane Detection Algorithm

  Authors

Mohamed Alshemi¹, Sherif Saif² and Mohamed Taher³, ¹Ain Shams University, Egypt, ¹STMicroelectronics, Cairo, Egypt, ²Electronics Research Institute, Egypt, ³Ain Shams University, Egypt

  Abstract

The two fundamental components of a complete computer vision system are detection and classification. The Lane detection algorithm, which is used in autonomous driving and smart vehicle systems, is within the computer vision detection area. In a sophisticated road environment, lane marking is the responsibility of the lane detection system. The warning system for a car that leaves its lane also heavily relies on lane detection. The two primary stages of the implemented lane detection algorithm are edge detection and line detection. In order to assess the trade-offs for latency, power consumption, and utilisation, we will compare the state-of-the-art implementation performance attained with both FPGA and GPU in this work. Our analysis highlights the benefits and drawbacks of the two systems.

  Keywords

Lane Detection, Computer Vision, FPGA, GPU, CUDA.